Very large scale integrated (VLSI) semiconductor circuits are generally manufactured by depositing and patterning conductive and non-conductive layers on a substrate and by stacking these layers one on top of the other. As VLSI circuits become more sophisticated and more complex, the number of stacked layers or planes increases, thereby creating planarity problems. Much attention has been directed to solving this problem. By way of example, J. L. Freeman et al, in U.S. Pat. No. 5,149,674 provide a method for planarizing bonding and probe pads, and more particularly, multi-layer capture pads, in relation to the interior of the semiconductor VLSI devices.
A similar problem exists in packages onto which chips are attached, where although planarity has proven to present distinct advantages by better controlling critical dimensions and by more evenly distributing conductive and dielectric material, cost considerations may dictate maintaining a non-planar environment. This is particularly true for thin-film structures, and it is most evident in areas that surround vias. Vias are known in the art to establish electrical contact between wiring lines in one layer to wiring lines in some other layer, and to provide an external interface for interconnections. This contact can be maintained even if the lines to be contacted are not in adjacent planes, in which case contact is usually achieved by stacking vias one on top of the other. The process of stacking vias in a non-planar environment presents a problem in that vias display a dimple on the top surface usually caused by uneven deposition of the metal features. The dimple on the surface of a via causes a reduction in the surface area available for contact between vias, thus eliminating the use of stacked vias for process and reliability considerations. Moreover, when vias are stacked in a column, the effect of these dimples tends to compound, leading to a non-planar structure at the top surface.
Adding to the non-planarity problems, the manner in which a via column is laid out results in lines having non-uniform electrical characteristics due to the presence or absence of reference planes beneath or above the transmission lines. This unevenness causes a significant decrease in the uniformity of lines per channel for long wiring lengths.
Due to a non-planar environment, the design of the wiring layer and reference layers is critical since dielectric non-planarity introduces waviness in the lines that changes the electrical characteristics. The only viable method for maintaining uniform line characteristics is to have fixed areas in the layout for lines and fixed channels for wiring. This technique is used in a planar process to achieve uniformity by stacking the vias, thereby allocating specific areas for the vias and lines. Since vias in a non-planar process cannot be stacked and have interfaces with the lines, non-uniformity is thus produced both in the physical and electrical characteristics of the structure.